Processing at the Edge
Lattice/Modelsim simulations on Linux
Various steps required to setting up the Modelsim simulator packaged with the Lattice Radiant toolchain on Linux (specifically Ubuntu 20.04)
Lattice/Modelsim simulations on Linux
Various steps required to setting up the Modelsim simulator packaged with the Lattice Radiant toolchain on Linux (specifically Ubuntu 20.04)
A tiny module with a big pipe...
Check out this LinkedIn post on the latest product being developed at tinyVision. This is a 1"x1" System on Module featuring the newly announced Lattice Semiconductor CrosslinkU-NX33 FPGA with a...
A tiny module with a big pipe...
Check out this LinkedIn post on the latest product being developed at tinyVision. This is a 1"x1" System on Module featuring the newly announced Lattice Semiconductor CrosslinkU-NX33 FPGA with a...
Magic Smoke and PTC's
@stevenbell teaches a course in Introductory Digital Engineering at Tufts University and has bought many UPduino’s. He suggested that the ferrite bead be replaced with a PTC as he was seeing students shorting...
Magic Smoke and PTC's
@stevenbell teaches a course in Introductory Digital Engineering at Tufts University and has bought many UPduino’s. He suggested that the ferrite bead be replaced with a PTC as he was seeing students shorting...
tinyML talks: Low power Computer Vision meets t...
In this talk, Venkat dives into some of the practical issues facing the design and implementation of a Low Power Computer Vision enabled device. The recording for the talk is...
tinyML talks: Low power Computer Vision meets t...
In this talk, Venkat dives into some of the practical issues facing the design and implementation of a Low Power Computer Vision enabled device. The recording for the talk is...
Ground trampolines and Phase Locked Loops
A customer reported that the PLL on the UPduino low-cost Lattice iCE40 FPGA board was intermittent. The blog details the process I used to debug the issue. This work in part...
Ground trampolines and Phase Locked Loops
A customer reported that the PLL on the UPduino low-cost Lattice iCE40 FPGA board was intermittent. The blog details the process I used to debug the issue. This work in part...