Overview
Many times, we need to connect multiple cameras to a host device using s single UVC bridge. Think about industrial robots, surgical devices, drones, security applications etc. However, there is no solution available in the market that can take multiple MIPI sensor inputs and interface directly to UVC without adding an intermediate FPGA. This leads to added cost, area and power.
At tinyVision.ai, we've built a multi-camera solution that overcomes this limitation. Our solution is the first to support a dual (and more!) camera stream using a single FPGA leading to reduced cost, area and overall power.
The overall architecture is shown below:
Features
- Bridges MIPI signals to UVC streams, supports 1, 2, 4 Lane MIPI CSI-2 up to 1.2Gbps/lane
- Supports single or dual camera configurations at up to 3.5Gbps total throughput.
- USB Data plane is completely handled by the FPGA RTL resulting in minimal latency, jitter and deterministic behavior.
- Complete reference design is provided to show how to interface one or two Raspberry Pi camera modules (IMX219) to the FPGA, 1920x1080/30 fps each along with simple ISP implementations for Debayer and Auto Exposure/Gain/White Balance. Optional Frame sync between sensors can be implemented on the FPGA.
- Zephyr RTOS support is provided to allow for easy integration into existing systems and additional application/sensor development/integration.
- Optional 800MBps memory controller to enable frame-buffer based applications such as image processing.
- Supported by the Streamlogic Design Suite for no-code GUI based image processing algorithm implementations on the FPGA.
FPGA Utilization
The following table shows the FPGA utilization for the single-camera MIPI2UVC IP.
| Resource | Used | Total | Percentage |
|---|---|---|---|
| LUT4 | 3450 | 27648 | 12.5% |
| FFs | 2310 | 27801 | 8.3% |
| BRAMs | 11 | 64 | 17% |
| DSPs | 0 | 64 | 0% |
| LRAM | 2 | 5 | 40% |
Dual-Camera Reference Design
The following table shows the FPGA utilization for the dual-camera MIPI2UVC IP.
| Resource | Used | Total | Percentage |
|---|---|---|---|
| LUT4 | 6104 | 27648 | 22% |
| FFs | 3890 | 27801 | 14% |
| BRAMs | 13 | 64 | 20% |
| DSPs | 0 | 64 | 0% |
| LRAM | 2 | 5 | 40% |
Supported hardware
The MIPI2UVC IP is designed as a data mover with a 64 bit FIFO interface for the high bandwidth data streams. The data-mover engine itself can be utilized for any applications requiring movement of data between peripherals and a main processor using either IN or OUT Endpoints. We currently use this in our reference design to move data between the MIPI2UVC IP and the host using IN endpoints. The IP can be easily customized to support OUT endpoints as well for display or other such applications (Instrumentation, Radios, etc.).
The IP is accompanied by a complete reference design supporting dual 1920x1080/30 fps streams. Supported hardware includes the tinyVision.ai tinyCLUNX33 platform and the Lattice CrosslinkU-NX33 reference design.
Related products:
tinyCLUNX33 System-on-Module
Applications
The MIPI2UVC IP is usable in a variety of applications requiring camera aggregation such as Robotics, Security, Medical Imaging, and Industrial Automation and test equipment.